Simple algorithms can be analytically characterized, but such analysis is questionable or even impossible for more complicated algorithms, such as Model Predictive Control (MPC). Usually the end user of a processor that carries out the arithmetic operations of MPC, works at a high level of abstraction; thus he/she is unaware of the underlying limitations of the hardware and it is not possible to determine how accurate the result of a computation is. Instead, Monte Carlo Arithmetic (MCA) enables statistic experimentation with an algorithm in order to study its arithmetic behavior related to round-off errors and accuracy.

In MCA every approximate arithmetic operation is converted to an experiment by introducing a random unbiased error that models the rounding or truncation of a result more realistically than assuming the truncated bits are zero. This technique was utilized in [1] to study arithmetic algorithms implemented on a Floating-Point number unit. In this work we study the arithmetic properties of the Logarithmic Number System (LNS) in conjunction with MCA, which form the MCLNS.

The knowledge of the accuracy becomes more imperative when MPC is used for control problems of small-physical size where the wordlength of the underlying hardware is reduced in order to increase the performance and save area, power consumption and cost [2, 3, 4]. The direct drawback of the reduced accuracy is the increased susceptibility of the circuit to round-off errors that accumulate with consecutive arithmetic operations (especially for ill-conditioned problems), and increased occurrence of overflows and underflows. Another side effect of reduced-precision arithmetic is the increased probability of the appearance of catastrophic cancellation.

Utilizing MPC requires a hardware implementation capable of carrying the computational burden of the algorithm in real time on a reduced-area footprint. In [2] an architecture is proposed based on a microprocessor combined with a matrix coprocessor capable of efficient execution of the arithmetic operations of an MPC algorithm in real time. For this implementation the underlying hardware utilizes a 16-bit LNS unit to carry out the arithmetic operations.

Using this hardware platform, in [5] it was shown how MCA can be used to mitigate the effects of catastrophic cancellation and ill-conditioned matrices. In this work we extend the use of MCA to studying, by simulation, MPC's arithmetic stability and to establish a relationship between the distribution of the expected results and the wordlength used on the LNS arithmetic unit.

[1] S. Parker, B. Pierce, P. Eggert, “Monte Carlo Arithmetic: How to Gamble with Floating Point and Win,” Computing in Science & Engineering, Vol. 2, No. 4, pp. 58–68, July/August 2000.

[2] P. Vouzis, L. Bleris, M. Kothare, M. Arnold, “A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control,” Submitted to the IEEE Transactions on Control Systems Technology (2006).

[3] L. G. Bleris, J. G. Garcia, M. V. Kothare, and M. G. Arnold, “Towards Embedded Model Predictive Control for System-on-a-Chip Applications,” Journal of Process Control, vol. 16, pp. 255–264, March 2006.

[4] R. S. Parker, F. J. D. III, and N. A. Peppas, “A Model-Based Algorithm for Blood Glucose Control in Type I Diabetic Patients,” IEEE Transactions on Biomedical Engineering, vol. 46, pp. 148–56, Feb. 1999.

[5] P. Vouzis, M. V. Kothare, and M. Arnold, “Evaluating Robustness of Embedded Model Predictive Control Using Monte Carlo Simulation,” AIChE annual meeting, San Francisco, CA, Nov. 2006.

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