The scaling of CMOS transistors calls for smaller features and ultra low-k materials. Among the available low-k materials, using air as the dielectric has the best electrical performance for intra-level interconnect. Improvements in the air-gap structure created by the thermal decomposition of a sacrificial polymer have been investigated. The fabrication processes of air-gaps/Cu interconnect structures for 200 nm half pitch and the aspect ratio of 2.0 were developed and demonstrated. The measured capacitance of air-gaps/Cu interconnect structures was 42% smaller than that of SiO₂ dielectric, and the k_eff of air-gaps was 2.4. Fringing in the oxide above and below the air-gap raises the total capacitance above that of air (ε_r=1). As the distance between the two adjacent metal lines becomes smaller, the capacitance increases due to an increase in the fringing field. The effect of extending the air cavity into the inter-level dielectric region further reduces the effective dielectric constant. Extending the air-gaps/Cu interconnect structures into the inter-level region by 100 nm decreased the capacitance by 46% compared to SiO₂, and the k_eff of extended air-gaps was 2.2. In addition, the moisture uptake of air-gaps/Cu interconnect structure was studied.