According to Semiconductor Industry Association (SIA), global sales of semiconductors reached $247.7 billion in 2006, an increase of 8.9 percent from the $227.5 billion reported in 2005 [1]. Due to the increasing consumer demand for smaller computers that process data at a much faster rate, processors that have a large number of transistors per chip are required. For example, Intel ItaniumŽ 2 uses as many as 1.7 billion transistors operating at 1.6 GHz [2]. However, further miniaturization is restricted by poor thermal conductivity of silicon. Carbon nanotubes have nanoscale dimensions (1-2 nm for single-walled; 10-20 nm for multiwalled) and are a promising candidate for creating smaller transistors. Carbon nanotube field-effect transistors (CNTFETs), introduced by IBM in 1998, were made by dispersing carbon nanotubes by sonication in a dichloroethane solution, and then spreading them on a substrate with predefined electrodes [3]. While this technique demonstrated the feasibility of CNTFETs, the processing limited the number of transistors per chip. Therefore, a novel processing technique is needed to efficiently and effectively produce commercial CNTFETs.

Controlled parallel growth of CNTFETs in-situ is a way to solve the processing difficulties to make many CNTFETs A process is being developed that combines nanoscale patterning by e-beam lithography with the controlled growth of CNTs demonstrated by Bazzana [4]. This process will control the placement of Ni nanoparticles using e-beam lithography to modify surface free energy, and control the growth sites and directionality of CNTs. First, troughs (1 μm × 30 nm × 25 nm each, 110 μm spacing between 2 troughs) were made by e-beam lithography on the Si substrate with 100 nm thick SiO₂ on top. A gold electrode (100 μm × 100 μm × 50 nm) was patterned at both ends of each trough. Ni nanoparticles were deposited to make sites for CNTs in troughs between electrodes. Initial results show the ability to fabricate many CNTFETs at once, with controlled directionality of carbon nanotubes.

1. Semiconductor Industry Association (SIA) report, February 2, 2007 (http://www.sia-online.org/pre_release.cfm?ID=426).

2. Intel Technology Update (http://h20223.www2.hp.com/NonStopComputing/downloads/Silicon%20Giant.pdf)

3. Martel, R., T. Schmidt, H. R. Shea, T. Hertel, and Ph. Avouris, Single- and multi-wall carbon nanotube field-effect transistors, Appl. Phys. Lett., Volume 73, pp. 2447-2449, 1998.

4. Bazzana, S., Ph.D. Thesis, Northeastern University, Boston, 2004.